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Le Duck!

And so, finally, things are wrapping-up and my 1-year chip-design "military service" is coming to an end. But hey, where am I going without this little fella :)

Le Duck!

Check out some more here.

Date:Sun Mar 29 16:45:47 CET 2016

A SKILL script to check and save all

Have you ever had this irritating issue with multiple unsaved schematic diagrams lower in the hierarchy preventing you from netlisting? Well, now we have a solution. Just bind that function to a handy key and blow the whistle when in trouble :)

; Checks and saves all cells in a given library name,
; Initial version A - Deyan Levski, 19.08.2015
;
;

procedure( checkAndSave(libName)
notSave = '()
lib     = ddGetObj( libName )
println(libName)
println(lib~>name)
cellList = lib~>cells~>name
foreach( cell cellList
cellview = dbOpenCellViewByType( libName cell "schematic" "" "a" )
if(cellview != nil then
schCheck(cellview)
dbSave(cellview)
dbClose(cellview)
println(cell)
println("saved")
else
notSave = append1(notSave cell)
)
)
println("Cells not checked:")
) ; procedure


A hint: you can use " libName = geGetEditCellView()~>libName " to automatically fetch the library name you are currently in.

Date:Sun Mar 26 22:34:47 CET 2016

Highlights from the image sensors session at ISSCC 2016

I thought that it might be a good idea to share the visuals from ISSCC with you and give short comments on some of the works I found intriguing from the CIS section. Please disregard my punctuation and language, this initially used to be a brief e-mail to my coworkers, however, I thought, "Why not get a free post out of it?" :) Unfortunately I am not allowed to upload any of the materials I sent them, thus you will have to refer to the original papers at IEEE XPlore.

Some new imaging materials made it to the CIS section this year, in particular there were two intriguing papers from Panasonic presenting an organic photoconductive global shutter imager with 120dB DR and speed of 60fps at almost 1MP with quite low read noise too!!! Also, note - they report a 600ke- FW capacity for a 6x6um pixel - impressive! There was a live demonstration of the imager, which looked rather sneaky as they used a very bright light (car headlamp) for illumination, which suggests low quantum efficiency of the sensor. Unfortunately, Panasonic did not provide any further comments on their work, apart from what is there in the slides. Some people asked direct questions on QE and process - answers were simply "I don't know".
The original paper is entitled as: An Over 120dB Simultaneous-Capture Wide-Dynamic-Range 1.6e- Ultra-Low-Reset-Noise Organic-Photoconductive-Film CMOS Image Sensor

Jan Bogaerts from CMOSIS presented an almost 400MP imager for airborne mapping, working at 1fps in 14-bit mode. Really impressive work from an engineering point of view. I managed to get hold of the sensor which has the size of a large smartphone, and one can clearly see the 6x3 pixel die blocks stitched together. The imager has no color filters, however the whole system uses 6 additional CCD sensors for color information extraction and a quite sophisticated optical stabilization system.
For more details refer to: 105x65mm2 391Mpixel CMOS Image Sensor with >78dB Dynamic Range for Airborne Mapping Applications

David Stoppa presented two works on SPAD imagers, one of which you can find in the visuals. The other presentation was given at a forum and have no electronic slides to show. The impressive point within these SPAD projects is that they report a read noise as low as 0.22 e-. This in terms allows them to measure photon shot noise and observe its poisson distribution! Theoretical physics works!
Paper title: A 64x64-Pixel Digital Silicon Photomultiplier Direct ToF Sensor with 100MPhotons/s/pixel Background Rejection and Imaging/Altimeter Mode with 0.14% Precision up to 6km for Spacecraft Navigation and Landing

TSMC, Toshiba and NHK presented works focusing on the ADC and analog signal processing in 3D stacked chips. Although, NHK and Toshiba present a refined version of their old cyclic ADC architecture, it is still worth noting that they report pure conversion time speeds of less than 0.9us, with relatively low energy per conversion. TSMC show detailed schematics of their Gray-coded ramp ADC, worth having a deeper investigation.
Paper titles accordingly: A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA; A 1.1um 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters

In addition TSMC's work features an interesting readout technique named "Negative Substrate Bias Readout" - In simple words: by biasing the substrate negatively they can use 1.5V supply for the readout and still get 3.3 volts for the pixel diode - thus saving power and not compromising SNR. This technique is enabled by the 3D stacking as the pixel array is a separate die, which can have a separate substrate bias.
Ref: A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias

For more information and details around the presented works, I suggest having a further look at the digest materials here.

Date:Sun Feb 13 21:04:23 CET 2016

Simple time logging in #!/bin/sh

Time tracking has always been an important measurement, especially for employers and supervisors. While starting with my doctorate studies I wrote a simple time logging script which I intended to use daily at the very beginning. There's tons of already written software for time tracking, management, optimization, boosting efficiency, creativity, spring daisies and so on... I wanted something extremely simple, Microsoft-Project-kind-of-software makes me sick. That's why I decided to get a basic mechanism, just like the old punch machines. Unfortunately, things changed a little bit and the need of using time tracking smeared-out... hmmm... really, there is no point in tracking time...

Anyway...So... --->>> Here... ---> | time.sh | <--- The script accepts two arguments:

First argument: either in or out

Second argument: a comment, let me give you an example. When I go to the lab I open a shell and write:

punch in Arrived early today, the neighbour's rooster woke me up at 6 a.m. ... I should cook a chicken soup rather soonish...
punch out Lunch!
punch in Let's get that charge pump pumping
punch out Sumo de laranja natural por favor :D
...


Alternatively you can also type "punch see" to get a list of your timestamps.

The command is called punch for historical reasons. I have simply added a symbolic link named punch in my /usr/bin folder which is pointing to the script. For the youngsters out there - have a look at punch clock ;)

Date:Sun Dec 05 18:56:14 CET 2015

Recently, I conducted a quick investigation on esoteric ADC architectures which have probably never left the testchip arena, or if they have, we do not know much about it due to the usual corporate masquerade policies. I want to throw my collection of links to you readers and try to popularize the otherwise very niche field.

One of the esoteric, or rather unexplored areas of ADCs is beta-expansion number representation. Beta-expansion is practically a complex way of saying a non-integer radix number usually falling between radix 1 and 2 when we talk about it in the context of ADCs. Other synonym terms can also be found, such as: "golden ratio encoder", "beta encoder", "non-integer encoder", "flaky quantizer" etc...

The beta encoding technique is mainly applicable to residual types of ADCs such as the pipelined, cyclic and SAR ADCs. It may be that it is also applied to some of the other types of existing ADC architectures however, I am not aware how it could be used in an integrating or flash ADC for example. To make this post more informative, let me give you a brief example of beta quantizers with a pipelined ADC. Here is the transfer function of a 1.5 bit/stage MDAC:

You can see that there is already added redundancy of 0.5 bits, which together with the classic back-end digital error correction algorithm works very efficiently in getting rid of the offset errors in the comparators and MDAC OTA, to up to levels of 1/4 the reference voltage. The figure above isolated only the offset errors, now if we look at the produced gain errors from the OTA and capacitors in the MDAC we get a different form of transfer function distortion:

It is quite clear that the classic stage-redundancy-based digital error correction would not work in the case of residue gain errors, so we would get some rather nasty DNL code gaps. It is very important to mention here that gain errors in the MDAC stage, result in radix deformations in the converted values. These deformations could be tilting towards either higher or lower than radix-2 digital number, usually dependent on capacitor matching and OTA gain.

So if we know that the radix is linearly shifted, we could technically try to correct it with a single multiplication. Here comes the beta-encoding part, which aims to modify the MDAC in advance such that it is intentionally producing redundant code i.e. having a radix lower than 2. Radixes higher than 2 result in binary code gaps which are non-correctable and have no redundancy. Designing for a lower radix code means that we could use a constant-low-gain OTA and intentionally mismatched sampling capacitors in the MDAC. The uncorrected output of such a converter would then look more like in the figure below:

Thus, if we measure two points from the ADC's transfer function (A and B) we can determine the produced radix by using an iterative method. The radix error based on our swept radix search parameter $\beta_{sw}$ and the two points (A and B) from the transfer curve of the ADC would be: $$\sigma(\beta) = \sum_{n=1}^{n=12} (D_{n_{A}} - D_{n_{B}})\frac{1}{\beta_{i}}$$

That fancy equation tells us that the radix shift is linear and can be determined, we have only two points... The non-linearity shown on the graph below comes from $\beta_{i}$ which is our estimation/guess. Beta codes show redundant patterns which is why we see that non-linearity in the radix estimation error.

Once we have estimated the radix, we can apply conventional floating-point multiplication to bring back the A/D converted code to radix-2. All of the above sounds like a great idea, but hmmm...

1) We got rid of the high gain requirement in the OTA, but pushed the problem into designing a constant-low-gain OTA. Which is nearly as non-trivial as designing a very high gain OTA.

2) In the case of a pipelined ADC, capacitor mismatch between the stages is still an issue.

3) In the case of a cyclic ADC the beta-encoding technique might actually work well, as we have a single capacitor pair for all conversions

4) Requires a costly floating-point multiplication as well as an initial radix estimation and coefficient storage

5) 4) makes the implementation in an ADC array nearly impossible, or not worth due to the huge number of coefficients and multiplications required

All of the above facts make the classic beta expansion technique at first sight not extremely attractive, however some of the properties of redundant codes make them worth having a deeper look. There has been ongoing research on beta expansion for a while now and I sincerely hope that it would continue in the future. Here is my list of collected links on the topic:

Papers:

Boris Murmann, On the use of redundancy in Successive Approximation A/D Converters

Daubechies et. al., Beta Expansions: A new approach to digitally corrected A/D conversion

Suzuki et. al., Robust Cyclic ADC Architecture Based on Beta-Expansion

San et. al., Non-binary Pipeline Analog-to-Digital Converter Based on Beta-Expansion

Rachel Ward, On Robustness Properties of Beta Encoders and Golden Ratio Encoders

Biveroni et. al., On Sequential Analog-To-Digital Conversion with Low-Precision Components

Daubechies et. al., The Golden Ratio Encoder

Kohda et. al., Negative Beta Encoder

Pages:

The "Fibonacci Code" viewed as a Barcode

The "Fibonacci Code" viewed as a Serial Data Code

Conversion between Fibonacci Code and Integers

Finally, something pretty neat and "chaotic" :

Beta-expansion's Attractors Observed in A/D converters

Date:Sun Nov 22 17:53:23 CET 2015