**Dominant gate capacitance of a MOSFET**

These are simple concepts, which anyhow managed to play a trick on me while doing some SPICE simulations recently, so I decided to give a stress to this basic solid-state device model:

The complexity of MOSFET RC parasitics modelling can get extended to unprecedented levels, but when it comes to estimating the *gate* capacitance there is one node which is dominant. Unsurprisingly that's the capacitance associated with the polysilicon gate and the channel underneath which forms a kind of a parallel plate capacitor, it is usually denoted as **CG**. Let's revise some basic concepts, starting with the high-school physics relation for the capacitance of a parallel-plate voltage capacitor, where *A* is the plate area, and *d* is the distance between the plates:
$$C = \epsilon_{0}\epsilon_{n}\frac{A}{d}$$

This basic concept remains the same in MOSCAPs, except that the electrodes and their distance is modelled in a more unusual way. Now there are many other parasitics, such as the gate-source or gate-drain overlap capacitances, but these are usually orders of magnitude smaller than **CG**, and thus can typically be neglected in ballpark estimate calculations.

Here's a physical cross section view of a MOSFET, together with its **CG** plates.

The dominant gate capacitance of is formed by the gate (top plate) and the charge carriers in the channel underneath, all sandwiched between the gate oxide SiO2. The top plate is electrically (conductively) fixed, while the equivalent bottom plate appears as if it is floating. This is due to the variable space-charge distribution under the channel. This modulates the effective distance between the two plates with varying gate-bulk potential. The charge density in the semiconductor underneath the gate usually follows the following function (as seen on the surface).

When the **dominant charge carriers**, as for example **holes** in a **p-type** semiconductor, have migrated under the channel with a high density, due to the applied electric field, the device is operated in **accumulation**. On the other hand, a strong reversal of the gate potential forces the **minority charge carriers** to drift underneath the gate and form an area with high **electron** density. This mode of operation is referred to as **inversion**. In a MOSFET device, both operating modes, when operated under sufficiently high electric fields, force the carriers to form a gradient in the channel, which has a fairly similar distance between the gate dielectric. However, when the MOSFET is operated under weak inversion, the space-charge density forming the bottom plate electrode is nonlinear, and this is the place where things start to become a bit complicated.

When the surface potential is close to zero, the concentration of both carriers remains in a somewhat diluted state, this is indicated under the depletion section in the figure. When the surface potential approaches to form a channel, a weak electron inversion layer is formed. Because of this, the bottom plate of the gate capacitor floats. This forms an additional capacitor in series with the gate oxide capacitor, which varies greatly with the electrostatic potential. Quantitatively speaking the dependence of **CG** as a function of the electrostatic potential in a MOSFET behaves as shown in the classic diagram below.

The diagram has similarities with the space-charge density diagram and shows a capacitance versus gate voltage of a p-type MOSFET. Three operation modes can be identified.

**CV CHARACTERISTICS: ACCUMULATION**

When the gate voltage (relative to the bulk in a p-sub device) is negative, the channel is in accumulation. Per rule of thumb, the capacitance in accumulation approaches the one of Cox when the gate voltage is more negative than the so called flatband voltage. Vfb is a potential when there is no charge present on the oxide, or the oxide-semiconductor interface. In the case of weak accumulation the gate capacitance follows the relation

$$\frac{1}{C_{g}} = \frac{1}{C_{ox}}\bigg(1 + \frac{2kT/q}{V_{g} - V_{fb}}\bigg)$$Since 2kT/q is 0.052 V, Cg quickly approaches Cox at gate bias of lesser than -0.5 V.

**CV CHARACTERISTICS: DEPLETION**

When the gate bias is slightly higher than Vfb, in the case of a p-type substrate, the channel surface starts to get depleted of holes. The effective bottom plate of the MOS thus spreads out to the inner section of the substrate, this has an effect of increasing the equivalent plate-to-plate distance. As a result the Cg exhibits a decrease. The effective series capacitance caused by channel surface depletion can be approximated as

$$ C_{d} = \frac{\epsilon_{si}}{d_{dep}} $$where $d_{dep}$ is the equivalent depletion width and $\epsilon_{si}$ is the effective dielectric permittivity of the depleted region. Unfortunately its calculation is rather involving and is not particularly practical in ballpark designs. The total gate capacitance in the case of a depleted channel surface can be approximated to

$$C_{g} = \frac{C_{ox}}{\sqrt{1 + (2C_{ox}^{2}(V_{g}-V_{fb}/\epsilon_{si}qN_{a}))}}$$where $N_{a}$ is the acceptor concentration of the bulk silicon, and $\epsilon_{si}$ is the effective dielectric permittivity of the depletion region. It should be noted that this expression is an approximation and describes the gate capacitance in very weak inversion. This is also the point where Cg is of lowest magnitude.

**CV CHARACTERISTICS: INVERSION**

When the gate voltage increases further, typically around and above Vth, the gate capacitance stops decreasing as the depletion region slowly vanishes. Instead an inversion layer is formed, which in the case of a p-type semiconductor is comprised of electrons diffusing up the gate electrode. In effect, the bottom plate (formed by the electron channel) moves closer to the top polysilicon gate, which increases the gate capacitance. In very strong inversion Cg approaches that of Cox. Not surprisingly, the gate capacitance in strong inversion is also given by the relation expressed for accumulation. Repeated here for convenience

$$\frac{1}{C_{g}} = \frac{1}{C_{ox}}\bigg(1 + \frac{2kT/q}{V_{g} - V_{fb}}\bigg)$$The above relations however, are typically valid for the case of low-frequency DC signals. High frequency signals experience a different equivalent gate capacitance. This is due to the varying depletion capacitance, which is due to the limiter charge carrier mobility and their diffusion inertia.

Finally, this is just a top-of-the-line basics, more in-depth theory can be found in the excellent book: Solid-State-Electronic-Devices (6th edition), by Ben Streetman and Sanjay Banerjee. Also, Modern VLSI devices, by Yuan Taur and Tak Ning is also a very good resource.