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A quick review of Time-to-Digital Converter architectures

I have been recently looking at various ADC architectures employing coarse-fine interpolation methods using TDCs, so I thought I'd share a quick list with brief explanation of the most common TDC architectures.

1. Counter based TDC – Probably the simplest method to digitize a time interval is by using a stopcounter. Counter based TDCs use a reference clock oscillator and asynchronous binary counters controlled by a start and a stop pulse. A simple timing diagram depicting the counter method's principle of operation is shown below:

Counter based TDC principle of operation

The time resolution of counter based TDCs is determined by the oscillator frequency and its quantization error is generally dependent on the clock period. Counter method TDCs offer a virtually unlimited dynamic range, as with the addition of a single bit the counter's capacity is doubled. This comes at the cost of an increased quantization error. The start signal can be either synchronous or asynchronous with the clock. In the case of an asynchronous start and stop pulses its quantization error can be totally random. Similarly if the start pulse is synchronous with the clock, this TDCs' quantization error is fully deterministic, if we exclude second order effects from clock and start pulse jitter respectively. With current CMOS process nodes 45nm or so, the highest achievable resolutions vary in the order of a few nanoseconds to 200 picoseconds. The counter based TDC's resolution is generally limited by the reference clock frequency stability and the metastability and gate delay of the stop latches. To increase the counting speed an often reffered to as Double Data Rate (DDR) counting scheme can be employed, which uses a counter incrementing its value on both rising and falling edges of the count clock.

2. Nutt interpolated TDC (Time Intervalometer) – initially proposed by Ronald Nutt [1], the Nutt architecture is based on measuring the quantization errors formed in the counter method and subtracting these to form the final counter value. The sketch below depicts the basic principle of the Nutt method:

Principle of Nutt interpolation method

Typically a short-range TDC is used for synchronous fine quantization error measurement between the counter's clock and the stop pulse. The used short-range TDC as a fine quantizer can be of any type as long as its input range matches with the largest expected quantization error to be measured, which is the counter's clock period $T$. In case of the use of a Double Data Rate (DDR) counter the input range is reduced to $T/2$. The global TDC presicion of a TDC employing the counter scheme with Nutt interpolation is improved by a factor of $2^{M}$ where M is the resolution of the fine TDC in bits.

The challenges the design of Nutt interpolator based TDCs are generally linked with the difficulty of matching the gain of the fine TDC with the clock period of the coarse counter. Both INL and DNL of the fine interpolation TDC is translated as a static DNL error at the combined output. Moreover, any noise in the fine TDC also translates as a DNL error in the final TDC value, which creates a non-deterministinc DNL error performance which cannot be corrected for.

3. Flash TDC – This is probably one of the simplest short-range TDC architectures. It uses a clock delay line and a set of flip flops controlled by the stop pulse for strobing the phase-delayed start pulse.

Basic Flash TDC core architecture

It can be employed in a standalone asynchronous scheme, where the start pulse is fed to the delay line and the stop pulse gates the flip flops. Alternatively it can be used as an interpolator to the counter scheme, in which case it's start pulse is controlled by the low-frequency count clock. In the case of the last configuration it is important that the sum of the delays in the delay line matches with the clock period $T$, or $T/2$ in the case of a DDR counting scheme.

Typically one way of delay synchronization is the deployment of a phase locked loop, which keeps the last delayed clock in-phase with the main count clock period. Usually the choice of delay number is based on binary sets of $2^{N}$. The strobed value in the flip flops is thermometer coded, which is consecutively converted to binary and added to the final value. Alternatively a scheme employing a ring oscillator incrementing the binary counter can also be used. In such schemes the complexity is moved from a PLL design to a constant-gain ring oscillator challenge.

An important aspect within Flash TDCs is that their time resolution is still limited to a single gate delay of the CMOS process.

4. Vernier TDC – The Vernier TDC, compared to Flash TDCs aims to improve the converter resolution beyond the gate delay limit. A principle diagram of a classic Vernier architecture is shown below:

Basic Vernier TDC core architecture

Two sets of delay chains with a phase difference are used, where the stop signal delays use a slightly smaller time delay. This causes the stop signal to slightly catch-up the start signal as it propagates through the delay line. The time resolution of Vernier TDCs is practically determined by the time difference between the delay lines $t_{res}=\tau_{1}-\tau_{2}$. If no gain calibration of the digitized value is intended, the choice of time delay and number of delay stages in Vernier TDCs should again be carefully considered. The chosen delay for the start pulse divided by the delay time difference should equal to the number of used delay stages, which to retain the binary coding, whould be $2^{N}$.

$$\frac{t_{ds}}{t_{d}}=N$$

The Vernier TDC principle is inspired by the secondary scale in calipers and micrometers for fine resolution measurements. It was invented by the French mathematician Pierre Vernier [2].

5. Time-to-Voltage Converter + ADC – the TVC architecture converts time interval into votlage. It is difficult to achieve a high time resolution with such schemes as traditionally the only reasonable way of converting time into voltage is by using a current integrator in which a capacitor is charged with constant current for the duration of the measured time interval.

Basic principle of TVC TDCs

After the time measurement is complete, a traditional ADC is used to quantize the integrated voltage on the capacitor.

These architectures could be used in applications where a mid- or large time measurement ranges are required. For practical reasons, the TVC type TDCs do not suit well as a time interpolator combined with counter based TDCs. The noise and linearity difficulties in current integrators for high speeds are setting a high lower bound for the time dynamic range of TVCs.

6. Time Differenec Amplifier based TDC – one concept for time difference amplification (TDA) in the digital domain is introduced by Abbas et al. [3]. An analog time stretcher allows for resolution improvement by amplifying the input time interval and successively converting it with a lower resolution TDC. The concept is similar to the analog voltage gain stages placed at the input of ADCs. A time amplifier based on the originally reported by Abbas et at. architecture [3] is shown below:

TDA principle and a basic TDA cell

The circuit represents a winner-takes-it-all scheme, where the gates are forced in a metastable state performing a mutual exclusion operation, the consecutive output inverters apply regenerative gain to the MUTEX element. By using two MUTEX elements linked with the start and stop signal in parallel, with a time offset and then edge-combining their outputs one can amplify the initial edge's time difference. The difference in the output voltages of a bistable element in metastability is approximately $\Delta_{V} = \theta.\Delta_{t}.e^{1/\tau}$, where $\tau$ is the intrinsic gate time constant, $\theta$ the conversion factor from time to initial voltage change at the metastable nodes and $\Delta_{t}$ is the incoming pulse time difference [4]. We can note that the output rate of change at the metastable node is exponenitally dependent. Thus, if we intentionally delay "forwards" and "backwards" in time two MUTEX elements and combine their edges, we would acquire a linear time difference amplification caused by the logical edge combination. The output time difference in the corresponding case would be equal to $\Delta_{out} = \tau . ln(Td + \Delta_{in}) - \tau . ln(Td - \Delta_{in})$. Several different variations of the latter circuit exist, most of which base on the logarithmic voltage dependency of latches in metastable state.

All time difference amplifier TDC approaches impose challenges related to the linearity of TDAs as well as their usually limited amplification factors.

7. Successive approximation TDC – this architecture uses the binary search algorithm to resolve a time interval. A principle diagram of a 4-bit binary search TDC is shown, as presented by Miyashita et al. [5].

Successive approximation TDC architecture

Imagine that the stop pulse slightly leads the start pulse with time difference of $\Delta = 1.5\tau$. The arbiter D3 would then detect a lead and reconfigure the multiplexer delays such that they lag the start signal by $4\tau$, thus leading to a difference of $2.5\tau$. The resolved MSB in that case would be the inverted value of D3, or '0'. Further on, arbiter D2 detects a lead in the start pulse over the stop by $2.5\tau$, in which case it would reconfigure the multiplexer delays in stage two to lag the stop signal by $2\tau$. The MSB-1 value is the inverted value of D2 arbiter which would thus be '1'. The MSB-2 value would be equal to 0, respectively, as the stop signal now leads with $0.5\tau$. Finally, arbiter D0 dechipers a '1' due to the start signal now leading with $0.5\tau$.

This topology effectively utilizes a time-domain SAR scheme and has a time resolution of $\tau$. Open-loop binary search schemes as the propsed here [5] require good matching between the delay elements, which typically suffer from low PSRR. Nevertheless, this SAR scheme is relatively new to the TDC world and might provide us with promising food for future research. Compared to the Flash TDC, the SAR scheme offers a $2^{N}-N$ reduction of strobe latches.

8. Stochastic TDC – this family of TDCs uses the same core principle of operation as Flash TDCs, however, it is formed redundantly. Here is a sketch:

Principle diagram of a Stochastic TDC architecture

Because the Flash latches have an intrinsic threshold mismatch, they practically introduce a natural Gaussian dither into the resolution of each Flash bit. If we read out the values of all latches and average their values we can extract digitized values with sub quantized step resolution. In order take advantage of the oversampling, however, Flash TDCs require a large set of latches and delay elements, which comes at the cost of power. They are traditionally reserveed for DLL-type applications and often require a digital back-end calibration [6].

References:

[1] Ronald Nutt, Digital Time Intervalometer, Review of Scientific Instruments, 39, 1342-1345 (1968)

[2] Alistair Kwan, Vernier scales and other early devices for precise measurement, American Journal of Physics, 79, 368-373 (2011)

[3] A. M. Abas, A. Bystrov, D. J. Kinniment, O. V. Maevsky, G. Russell and A. V. Yakovlev, Time difference amplifier, in Electronics Letters, vol. 38, no. 23, pp. 1437-1438, 7 Nov 2002

[4] D. J. Kinniment, A. Bystrov and A. V. Yakovlev, Synchronization circuit performance, in IEEE Journal of Solid-State Circuits, vol. 37, no. 2, pp. 202-209, Feb. 2002

[5] D. Miyashita et al., An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing, in IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 73-83, Jan. 2014

[6] A. Samarah and A. C. Carusone, A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC, in IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1829-1841, Aug. 2013

Date:Thu Jul 21 17:24:54 CET 2016

Saleh
07 Nov 2016, 21:48
Dear DeyanLevski
Thanks for your attention to this field, and I appreciate for this good review, according to my knowledge there is also pipeline TDC structure that could be added to this review.
Regards
Deyan
07 Nov 2016, 22:43
Hello Saleh,

Thanks for your kind feedback. Yes, you are right, there is the pipelined TDC that is missing here. I also stumbled across a paper from a recent JSSC publication showing a ps resolution Cyclic TDC employing an analog (x2) delay element correction scheme:

Seo et al. A 1.25 ps Resolution 8b Cyclic TDC in 0.13 μm CMOS
http://dx.doi.org/10.1109/JSSC.2011.2176609

I've taken a note and I'll try to shape-up this post to reflect more architectures.
Saleh
05 Dec 2016, 22:22
Hello Deyan,
Thanks again for your attention to TDC, could you added to the quick reference or may be in another document about TDC specifications for example Bin size and resolution and their difference or single shot precision. I think there is no exact definition of them in the references. Also about ENOB that reported in some literatures.

Deyan
07 Dec 2016, 14:11
Yes, perhaps listing a table with the architectures' dynamic range, resolution, power etc might be a good idea. Been quite busy lately, although I'll try to get my hands onto it as soon as I get some fee time.

Thanks for pointing that out.
Saleh
12 Apr 2017, 01:24
Hello Deyan,
I wish to ask a question about the review about the TDC features, do you write it?
I also want to know exactly did you see any very low power TDC in Journals or any FoM that has a suitable description of TDC trades.