Currently there are just a few chip dissector enthusiasts sharing freely their findings with others. But two-three years ago, we didn't even have a single open chip database. Till this day the two biggest chip die microphotograph databases are zeptobars.ru and siliconpr0n.org. I was browsing around their chip database these days, and I am getting to see lots of inventive design approaches. Sometimes you can clearly identify that some chips have gone through several really messy metal mask fixes, and astonishingly such designs have still been shipped to mass production the way they are.
As the guys from siliconpr0n.org are providing their microphotographs under a creative commons commercial license (wow! even commercial! you guys rock!), I got tempted to use one of their chip photographs to create an infographic, denoting various details around the design. I chose a simple chip, which is a custom 65CX02 microcontroller used in a pocket game (it is not sure which one, tetris maybe?) using 3 Metal and 1 Poly process. It is hard for me to identify the exact process node, however, judging by the bonding pad size my guss is that it is somewhere around 0.8 um CMOS, if not even larger.
My first intention was to stick with red labels only, denoting analog design related details, however, as this chip is almost "purely digital" there is nothing much to comment, which lead to empty gaps. Well, I filled-in the gaps with blue labelling denoting my assumptions on the basic sub-blocks of this microcontroller.
The nicest detail I like about that chip is the tapered star connection at the bottom, which assures minimal noise on the oscillator circuitry, which is pretty much the only analog block in this microcontroller and uses the same digital supply as the rest of the core logic. Here's a zoom:
Some thoughts arose that it is clear — whoever designed this had an idea of what he was doing. Otherwise he could have easily merged the metal rails, it is easier to design it that way, so why bother splitting. Unfortunately it is not a very common scene, seeing pure layout engineers implementing such tricks at every level of abstraction in the design. In the case with this chip, it is kind-of clear that this was a decision taken at a top level.
On the left you can also see split power to the analog blocks as well. What is also interesting is that I can't identify passive ESD diodes for the power rails, what is visible though, is a tiny active ESD protection on top of the chip rail. It might be that parts of it are also circuits assuring correct power-on sequence, or it might be that there is power ESD but I am not seeing it under the metal padding.
I am leaving you now to explore more chips yourself in the databases.