Recent Pole-Zero Pairs
▨ Not deserted - temporarily stranded
▨ Analog-style digital design observations
▨ The semiconductor industry in Bulgaria Vol. 2
▨ Small-signal and large-signal MOSFET channel resistance
▨ Bricks and mortar of the internet
▨ Dominant gate capacitance of a MOSFET
▨ Mr. Sievert, a fictional character
▨ "This could be a very strong paper"
▨ Major milestone: Oxford thesis submission
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hey I'm still here
Hello internet! Just an update that I am still here, my place on the web is just slipping, ad interim. Since my last update in 2019 there has been a lot been going around. Due to one reason or another I have been unable to maintain my presence here, but light is yet to come.
In the past 3 years I was exposed to a wide spectrum of situations and encounters - both positive and negative. Overall, I most of my daytime hours were set aside to Photolitcs, while the rest I had to devote at setting order in place with other aspects of existence. During the summer of 2020 we received the first silicon of our flaghip sensor which resulted in some extra load for me. The experience as exciting as it was, was brimmed in ponders and disappointments. It turned out we had many issues with the freshly chiseled system which was giving me a hard time sleeping and calming down to reflect what was going on. As I was in a mode of full-swing debugging I had to slow down. I fell ill and had to be admitted to a hospital diagnosed with some unknown liver disorder. It took me over 6 months to recover fully and just as I came out of hospital, my father got diagnosed with a brain tumor and had to be operated urgently, but sadly could not make it. What dreadfulness did 20 and 21 deliver to me. What could have I done, but to keep the mill milling?
Some news from 2022. This July Photolitics turned 4 and our flagship image sensor is almost ready to be mass-produced. We have grown to a team of 11 people, all engineers in physics and electronics, and we continue to work on challenging projects, all at humane applications to better the world ever so slightly.
Recently, I passed the exam for a radio amateur class 2 license. It was organized and held by the CRC commission and the Bulgarian Federation of Radio Amateurs. Passing the exam meant going through a wide variety of radio communications ethics and etiquette manuals, but overall getting the class 2 license was easy peasy, and fun. I was given the callsign LZ2DLD (Lima Zulu Two Delta Lima Delta), and now can legally operate on the VHF and UHF bands with transmission power of up to 5 Watts.
Q3 and Q4 of the year would hopefully be as exciting as Q1 and Q2. Stay tuned, I think a short story might be coming soon.
Until then... 88 and 73
beyond a certain point mess is inevitable
How did I come to this? We were working on some messy digital circuitry which handles the output data stream of an image sensor and does some computations on it. Since I am not proficient with Place and Route tools (in fact have never done a PnR myself before) and don't have them available either, I faced the challenge of designing data pipelines and processing the old-fashioned analog-style digital design way. I am setting down a few observations here:
1. The human brain can only track a few variables at a time... Mine in particular seems to start getting confused when dealing with anything beyond 3.
2. Analog-style digital simulations takes longer to complete. By the time they are ready (SPICE), the neural network of an average homo sapiens would have forgotten what the bug was in the first place. Even if it's just 15 minutes - it's enough. Gate replacements with macros and VerilogA helps, and I should definitely write on the topic some other time.
3. RC in the clock/data path and retiming just complicates matter 10x.
4. Polygon pushing digital designs where timing needs to be obeyed can sometimes be a re-iterative process and a pain.
To pass the time while simulating you can contribute to your signal unconcentration by browsing the web. In my case, I found some immaculately organized pages on the history of VLSI design and also came across some old design files uploaded by Lynn Conway on her corner of the web. So let me share a tiny chip bit:
Impressive - an MPW back in 1978! From the history above it is evident that back in the day VLSI design used to be what Python coding is today - astonishingly popular amongst students. It has been so much harder back in the day, but excitement-spurred-motivation seems to have compensated for those difficulties. This document shows the working-out of the physical design rules for VLSI, as well as lists the gigantic list of projects placed on the 1979 MPC: array processors seem to have hyped in 1978, together with DMA controllers and associative memories - but really, what a lovely cocktail of digital circuitry. Oh, one last note there is also a project: an Inifinite precision multiplier - yeah if you had the inifinite memory!
It is heartwarming to see that LiTH has joined the MPC project just two years later, in 1980, to produce their first MPC in 1981. That's so so cool and likely few will understand! Now the graffiti under the tunnels between A and B house start to make sense.
is expanding... Silicon valley, brace brace brace :D
Awhile ago, precisely on August 14th 2017, I blogged on the state of the semiconductor industry in Bulgaria. The somewhat incomplete graphic diagram got surprisingly popular amongst various internet users. Thanks to their feedback I got some additional insight on the state of the industry as a whole. Now, I'd like to share an updated diagram and some extra news.
Here's what I think is a more representative diagram as of today, to the scope of my knowledge.
We can notice some differences with Version 1: firstly, the rumours that ASIC Depot exited through a sale to Broadcom were correct, and secondly, a fresh company has popped on the horizon - Photolitics, yes, that's us. Perhaps the only sole/core/purely bulgarian fabless design house in the country at the moment, also the first one in Northern Bulgaria too. The chart omits Smartcom from the list, as I don't consider them a pure-play design house, but rather a supporting custom design firm. The same applies to the LFoundry PDK team in Bulgaria too, not really pure spec-to-product chip design. Likely the same applies to ASIC Depot, but okay digital VLSI design is often rather scattered nowadays.
As with Photolitics, we are a team of 5 (soon to be six) analog gurus working towards a specific goal and standard product. Stay tuned for more, as I will dedicate a separate news release to us.
Lastly, if you know more on the topic or if you have found some inaccuracies let me know in the comments. It's highly likely that there is some information missing there.
When running SPICE DC simulations one could often see two types of MOSFET transistor operating point parameters for the channel resistance printed by the simulator. These often have different names depending on model versions spanning a range: ron, rout, rds, rd, 1/gds – these are at first sight ambiguous and could be a source of confusion. Usually one of them is much bigger than the other. Here is actually what each of them represents.
ron - this is the large-signal MOSFET channel resistance. This parameter is derived by the partial derivative of the current operating point versus a point where Vds = 0 and Ids = 0.
Even if trivial, worth noting here that we calculate ron by:
$$r_{on} = \left[ \frac{\partial v_{ds}}{\partial i_{ds}} \right]_{V_{gs} = \text{const}} $$Thus, for convenience I provide here a plot where the red line shows the partial derivative of the chosen point at the I-V curve, with respect to a 0 volts 0 amps operating point – this is in fact what is referred as ron. It is sometimes called large-signal resistance and it is calculated through the slope of the line connecting (0,0) with (vds,ids).
rout - this is the small-signal MOSFET channel resistance. Usually when running fixed operating point simulations we are interested in the small-signal resistance for the specific operating point. It is computed through the tangent line at (vds,ids), here is an example plot:
Looked at it the other way rout is vds over ids for a single point.
$$r_{out} = \left[ \frac{v_{ds}}{i_{ds}} \right]_{V_{gs} = \text{const}} $$The small-signal output resistance is usually the one needed for evaluating impedances of current sources etc... It is worth noting that $1/g_{ds}$ is effectively equivalent to $r_{out}$ and represents the small-signal conductance of the device.
