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Dominant gate capacitance of a MOSFET

These are simple concepts, which anyhow managed to play a trick on me while doing some SPICE simulations recently, so I decided to give a stress to this basic solid-state device model:

The complexity of MOSFET RC parasitics modelling can get extended to unprecedented levels, but when it comes to estimating the gate capacitance there is one node which is dominant. Unsurprisingly that's the capacitance associated with the polysilicon gate and the channel underneath which forms a kind of a parallel plate capacitor, it is usually denoted as CG. Let's revise some basic concepts, starting with the high-school physics relation for the capacitance of a parallel-plate voltage capacitor, where A is the plate area, and d is the distance between the plates: $$C = \epsilon_{0}\epsilon_{n}\frac{A}{d}$$

This basic concept remains the same in MOSCAPs, except that the electrodes and their distance is modelled in a more unusual way. Now there are many other parasitics, such as the gate-source or gate-drain overlap capacitances, but these are usually orders of magnitude smaller than CG, and thus can typically be neglected in ballpark estimate calculations.

Here's a physical cross section view of a MOSFET, together with its CG plates.

The dominant gate capacitance of is formed by the gate (top plate) and the charge carriers in the channel underneath, all sandwiched between the gate oxide SiO2. The top plate is electrically (conductively) fixed, while the equivalent bottom plate appears as if it is floating. This is due to the variable space-charge distribution under the channel. This modulates the effective distance between the two plates with varying gate-bulk potential. The charge density in the semiconductor underneath the gate usually follows the following function (as seen on the surface).

When the dominant charge carriers, as for example holes in a p-type semiconductor, have migrated under the channel with a high density, due to the applied electric field, the device is operated in accumulation. On the other hand, a strong reversal of the gate potential forces the minority charge carriers to drift underneath the gate and form an area with high electron density. This mode of operation is referred to as inversion. In a MOSFET device, both operating modes, when operated under sufficiently high electric fields, force the carriers to form a gradient in the channel, which has a fairly similar distance between the gate dielectric. However, when the MOSFET is operated under weak inversion, the space-charge density forming the bottom plate electrode is nonlinear, and this is the place where things start to become a bit complicated.

When the surface potential is close to zero, the concentration of both carriers remains in a somewhat diluted state, this is indicated under the depletion section in the figure. When the surface potential approaches to form a channel, a weak electron inversion layer is formed. Because of this, the bottom plate of the gate capacitor floats. This forms an additional capacitor in series with the gate oxide capacitor, which varies greatly with the electrostatic potential. Quantitatively speaking the dependence of CG as a function of the electrostatic potential in a MOSFET behaves as shown in the classic diagram below.

The diagram has similarities with the space-charge density diagram and shows a capacitance versus gate voltage of a p-type MOSFET. Three operation modes can be identified.

CV CHARACTERISTICS: ACCUMULATION

When the gate voltage (relative to the bulk in a p-sub device) is negative, the channel is in accumulation. Per rule of thumb, the capacitance in accumulation approaches the one of Cox when the gate voltage is more negative than the so called flatband voltage. Vfb is a potential when there is no charge present on the oxide, or the oxide-semiconductor interface. In the case of weak accumulation the gate capacitance follows the relation

$$\frac{1}{C_{g}} = \frac{1}{C_{ox}}\bigg(1 + \frac{2kT/q}{V_{g} - V_{fb}}\bigg)$$

Since 2kT/q is 0.052 V, Cg quickly approaches Cox at gate bias of lesser than -0.5 V.

CV CHARACTERISTICS: DEPLETION

When the gate bias is slightly higher than Vfb, in the case of a p-type substrate, the channel surface starts to get depleted of holes. The effective bottom plate of the MOS thus spreads out to the inner section of the substrate, this has an effect of increasing the equivalent plate-to-plate distance. As a result the Cg exhibits a decrease. The effective series capacitance caused by channel surface depletion can be approximated as

$$ C_{d} = \frac{\epsilon_{si}}{d_{dep}} $$

where $d_{dep}$ is the equivalent depletion width and $\epsilon_{si}$ is the effective dielectric permittivity of the depleted region. Unfortunately its calculation is rather involving and is not particularly practical in ballpark designs. The total gate capacitance in the case of a depleted channel surface can be approximated to

$$C_{g} = \frac{C_{ox}}{\sqrt{1 + (2C_{ox}^{2}(V_{g}-V_{fb}/\epsilon_{si}qN_{a}))}}$$

where $N_{a}$ is the acceptor concentration of the bulk silicon, and $\epsilon_{si}$ is the effective dielectric permittivity of the depletion region. It should be noted that this expression is an approximation and describes the gate capacitance in very weak inversion. This is also the point where Cg is of lowest magnitude.

CV CHARACTERISTICS: INVERSION

When the gate voltage increases further, typically around and above Vth, the gate capacitance stops decreasing as the depletion region slowly vanishes. Instead an inversion layer is formed, which in the case of a p-type semiconductor is comprised of electrons diffusing up the gate electrode. In effect, the bottom plate (formed by the electron channel) moves closer to the top polysilicon gate, which increases the gate capacitance. In very strong inversion Cg approaches that of Cox. Not surprisingly, the gate capacitance in strong inversion is also given by the relation expressed for accumulation. Repeated here for convenience

$$\frac{1}{C_{g}} = \frac{1}{C_{ox}}\bigg(1 + \frac{2kT/q}{V_{g} - V_{fb}}\bigg)$$

The above relations however, are typically valid for the case of low-frequency DC signals. High frequency signals experience a different equivalent gate capacitance. This is due to the varying depletion capacitance, which is due to the limiter charge carrier mobility and their diffusion inertia.

Finally, this is just a top-of-the-line basics, more in-depth theory can be found in the excellent book: Solid-State-Electronic-Devices (6th edition), by Ben Streetman and Sanjay Banerjee. Also, Modern VLSI devices, by Yuan Taur and Tak Ning is also a very good resource.

Date:Thu Jun 04 07:55:39 GMT 2018

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Mr. Sievert, a fictional character

A funny story. Today I happened to be around the lab used to inhabit back in 2014-2015 with Oscar and the MCAD lab ratz. A smudgy pic, here:

Back in the day Oscar was actively involved in a low-cost X-ray camera project that was supposedly going to make the world a better place. One of the challenges was to find vendors of some alien technology crystals, willing to collaborate on the project with us. As a very open and communicative guy it wasn't long after he found a few companies ready to send their quotes. Here is the place to mention that even a tiny chipped piece of these scintillating materials costs a fortune, so no sober company would have wanted to send out a free sample to a random guy at some university. Oscar kept bumping into a dead end with free sample denials which at some point led to his frustration. It was time to change strategy.

And so Mr. Sievert was born. As a professional in his 40s, Mr. Sievert was a successful manager in a prosperous company doing cutting-edge miracle devices for the medical industry. Coincidentially he happened to be doing this together with some folks from the local university. He was a confident man, who knew what he wanted, and if his project was successfull he was ready to order a stackfull of crystals. Mr. Sievert shared an office with the MCAD lab ratz, and also happened to have the same telephone number as them. See where I'm going? Oscar forged some clever fiction, just as we've been taught in academia.

It wasn't long after our phone transformed into some kind of a hotline receiving a few calls daily. Oscar now got showered with sample offers, most of them paid, but still, there was some free lunch from one company too, which in the end eventually led to the termination of his quest for scintillators. Unfortunately, the project was doomed from the very beginning as the core idea wasn't really feasible with the technology we wanted to use, which in itself is another comical story to cover some other time.

And so, the project was over. But hey, Mr. Sievert was not forgotten - at all. The phone kept ringing daily with people looking for an imaginary character that never existed, but shared a name with the great Rolf Maximilian Sievert. It was funny at the beginning as nobody in the lab except us knew what the Mr. Sievert story was about. In the summer of 2015 Oscar completely abandoned the X-ray project and moved over to an AI research lab, while I went to try my luck working in isolation on a tropical island. Mr. Sievert was long forgotten, or so we thought!

Two years later I came back to the same old lab. In the meanwhile the place got refurbished, people had changed, but the landline phone remained there. And so, during a hot summer day of 2017 the phone rang. As usual I waited a bit and picked up the phone, guess what?!

— Hello! This is Lisa calling from Ducky Duck Crystals Ltd. Can I speak to Mr. Sievert?

Date:Sat Apr 14 12:00:00 CET 2018

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"This could be a very strong paper"

Attenzione! Stark Zynismus ahead!

I'm at the department, drinking coffee in the common room while browsing the web.

All of a sudden my auditory sensors detect the phrase: "this could be a very strong paper"... The word combination drags my attention and curiosity — so I continue to listen:

— we should stack those thin-film elements, then complicate the study a bit more by measuring the temperature

— indeed, this could be a very strong paper

— we'll easily have it accepted at the international banana conference this fall

— let's enhance it a bit by adding a processor to measure and compute the data on-chip, real time, that'd be just cool to have

— yes yes, this could be a very strong paper

— finally we'll finish writing that other proposal, I've been so frustrated with this recently

That was just a regular ordinary postdoctoral researcher conversation on a Tuesday afternoon. Now my question to you reader is: What's wrong with this dialogue? I think the word stream in the yellow box above is so wrong, at so many different levels, that I just don't know where to begin.

I want to remain positive and don't really want to become one of those regular angry nerds bashing everything and blaming everyone. But, I just can't resist putting down a few thoughts about that crazy academic world.

Academics nowadays have become paper monsters, all they see is papers, they daydream of papers, their final work goals are solely focused on papers. Hence, we hear thought pathways such as: "this could be a very strong paper". Just imagine if the phrase was formulated as: "this could be very useful", or "if we're successful this could push the world be a better place". That'd be so cool to hear!

With all of that said, it's evident that a large chunk of academic research nowadays is corrupted. But why? I constantly seek meaningful explanations, but somehow I always get stuck. To be fair, looking at the past years and extrapolating back in time, it seems like, despite all of the junk work required to-be-alive by modern public schools, universities have brought about some genuinely remarkable discoveries. Though, I still think that these days research is better conducted in institutions other than universities, for which I scribbled some thoughts awhile ago, but for now let's get back to the topic and our yellow-boxed dialogue.

I'm looking at some data presented by Kendall Powell in his Nature article "The future of the postdoc". Ah well, Kendall's article does not point to a single reference supporting his plots, but let's just assume that the trend he states is about right. Have a look at the plot below. It shows some crude statistics about the number of postdocs as a function of time.

Active postdoc pile-up with years

So what do we have here? A generous four-times growth of active postdoctoral researcher positions in just 30 years. Now, take into account that usually there are a few, say, on average, 5 PhD students per postdoc, and you'll quickly see that the growth of PhDs throughout the years has followed a geometric progression. I think it's no surprise we see such a high number of poorly executed work. And I think that's not because the number of doctoral students has increased, but likely due to inefficient spendings. The whole system of grant applications and distribution has some flaws which nowadays drive scholars into writing science fiction in their applications to unprecedented levels.

I think here lies the answer to why the casual cafeteria dialogue. There is simply too much funding and too many researchers trying to get hold of it. Think of it as having a full pack of candy. The more you have, the more everybody wants to have of it, the more you're willing to give. The lesser the candy, the more cautious you are with giving it away.

But yeh, who am I to throw such wisdom, as I'm a part of the same crowd, and yet another guy from the pile of the to-be doctors.

Date:Thu Mar 18 10:30:08 GMT 2018

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Major milestone: Oxford thesis submission

Last year on July 18th I successfully passed my confirmation of status and was officially entiteled a DPhil candidate. During that hot summer day I had to set a my own final submission date for the thesis. I set March 9th, thinking that there's plenty of time to write up and finalize the thesis. Having to set such strict goals is kinda odd, I know, but the Oxford system is a but unusual in many ways.

Anyway, yesterday March 7th (just two days before the deadline), I submitted a copy of my thesis to the examination schools. Now that the examiner arrangements and hassles with timings, schedules, etc. are over, all I have to do is wait until they read my work and agree on a date for the official viva.

It's a bit early to be celebrating anything, as it is not yet known whether I would actually be given a degree or not, but I thought I'd put this here to mark that milestone. Here are some selected pictures from yesterday. Before going for a pint with colleagues at the Turf tavern, I had a decently long walk around university parks and Worcester college, which is a very peaceful place in the heart of the city. Looking at the ducks and the calm wildlife I realized that, actually, all of that PhD stuff is irrelevant. Life goes on, and the squirrels are happy with what they have: trees, acorns and sun... we should be too.

Date:Wed Mar 8 11:02:48 GMT 2018

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