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This post presents a quick investigation on the kickback noise problem in CIS ramp ADCs, and its assimilation with mass-spring-damper systems in theoretical mechanics.
In column-parallel ADC systems, the reference voltages are typically shared between all ADC slices. In the case of cyclic, SAR, and/or Sigma-Delta architectures, which use fixed DC reference voltages, it kind-of makes sense to try and minimize the ohmic resistance of the horizontally routed reference lines, so as to decrease the reference's settling time as much as possible.
State of-the-art Ramp ADCs, however, typically employ a local storage capacitor per each column which is initially reset to a reference starting point and then the latter (lumped capacitor) is slowly discharged via a global reference current source. The ramp ADCs are a special breed of data converters which distinguish themselves with two semi-discrete — semi-continuous-time modes of operation. The latter use continuous-time comparators which sense the slewing reference voltage (ramp) and toggle after it crosses the sampling point.
Now here's my motivation — no matter how much one tries to optimize the column comparator's input-pair for performance (see below), one normally ends up with some amount of charge, kicked back onto the ramp.
Kickback charge is almost linearly linked to the size of the diff pair and its load. The more we want to suppress 1/f noise, increase gain, the more kickback noise we end up absorbing on the reference voltage line. Normally! There are different types of active kickback noise reduction techniques for continuous-time comparators, usually implemented by load cut-off after comparison, passive cross-coupled bulks of the differential pair, active bias compensation, etc... Here we are focusing on the ramp reference voltage distribution line and what could we do with it to reduce the impact of kickback on the ramp.
Typically, the mitigation of kickback noise problems consists of designing a well-compensated comparator , and I do prefer these methods of root-cause elimination. However, exploring other approaches does not hurt either.
The following figure shows a typical column-parallel comparator configuration and their reference voltage line.
Imagine that all comparators have zero offset and they all have to convert the same voltage. Alternatively, imagine that there is just a slight variation between the voltages to be converted.
It appears that when one comparator kicks charge on the reference line, it is coupled next to the neighbouring comparators which may lead to an avalanche chain reaction. If the voltages to be converted differ just slightly (as is the case with a blank image and/or if we add natural comparator offset) then a kick in the center comparator, leads to a false trigger of the neighbour. This effect is also known as crosstalk.
Here is a simulation assuming an RC line with 1 mili Ohm column-to-column segments and 120 fF column capacitors. The kicked charge is highly exaggerated to amplify the effect, using 20 fF kick capacitor and almost infinitely steep step response on the cap of 1 Volt. Vramp_col1-7 shows the reference voltage line voltage at each column, and c1-c4 are the outputs of each column comparator (ideal and 4-total in this case), we can see that all toggle at the same time, meaning that the kicked charge will affect a high number of columns, in fact, all of them in this case.
If one increases the resistance of the reference voltage line to 1 Ohm per column, which is not unrealistic at all for a standard aluminium FSI CMOS process, we get a more dampened column-to-column variation.
By the use of high-resistance reference voltage line the columns are less coupled between each other. This, however, comes at the cost of bandwidth, which also alters the ramp magnitude per each column itself. You may notice that the ramps are no longer following the same voltage magnitude, but have a voltage offset instead. This offset would typically translate to ADC DN-offset, which may actually be cancelled by digital correlated double sampling. The ramp itself however, typically, for a fast ADC runs at about 1-2 us full-swing (e.g. 1.5 V). It means that the voltage line resistance cannot be increased very much as it violates the total ramp bandwidth. By using the open-circuit time constant method, the settling time of a ramp reference line would be:
$$\tau_{1} + \tau_{2} + \tau_{n} = C_{n}(R_{n-1} + R_{n}) + ... + C_{2}(R_{1} + R_{2}) + R_{n}C_{n} + ... + R_{1}C_{1}$$
Apart from the obvuous bandwidth problem, increasing the resistance of the reference voltage, would also mean that the reference current-to-voltage noise translation is also amplified. Which will be roughly proportional to the MOSFET current noise power (spot) times the sink resistance (i.e. refererence line):
$$V_{nref}^{2} \propto i_{nsource}^{2} r_{sink}$$
A good tip for checking the ramp's linearity and/or noise (assuming you run transient noise) is to actually plot its first derrivative and check for spikes (shown below).
You can see the kick on the ramp as a spike in the center, as well as the total ramp capacitor charge alternation resulting as a change in the mean magnitude of the derrivative (left-right handside of the bottom plot). Ideally, we expect to see a flat line. This method is well-known and very efficient in the analysis of linear systems.
Finally, the ramp crosstalk effect and damping can be transformed into a theoretical mechanics problem, comprised of mass-spring-damper elements:
The weights m1-m3 are coupled to the ramp in-column slew capacitors via a second small damper (the diff-pair parasitic capacitance). The coupling point is then additionally coupled columnwise via a spring which causes the chain crosstalk reaction. Anyone daring to solve the differential equations? How about making things more complex by modelling the kick-kick avalanche of all columns?
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