Photolitics

Photons Hit Electrons

Recent Pole-Zero Pairs

▨ Not deserted - temporarily stranded

▨ Analog-style digital design observations

▨ The semiconductor industry in Bulgaria Vol. 2

▨ Small-signal and large-signal MOSFET channel resistance

▨ Bricks and mortar of the internet

▨ Harvesting gamma radiation

▨ Dominant gate capacitance of a MOSFET

▨ Mr. Sievert, a fictional character

▨ "This could be a very strong paper"

▨ Major milestone: Oxford thesis submission

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Deep N-Well

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This work took a while, so I thought that it deserves a few words in the blogs. During the past year or so, I have been working on an image sensor ADC testchip. It was finally taped out yesterday! What's left now is some additional gastronomical work on the tapeout cake and the drainage of a rusty bottle of champagne.

The core of the testchip is a fast 12-bit column-parallel ramp ADC at 5u pitch, utilizing some special counting schemes to achieve the desired 1us ramp time at slow clock rates. Alongside, to be able to fully verify the pipelined CDS functionality and crosstalk, I've built a pixel array in line-scan configuration, some fast LVDS drivers, clock receivers, references, state machines, a few 8-bit iDACs, bond pads, ESD, and some other array-related stuff, all from scratch! The chip has a horizontal resolution of 1024 and 128 lines with RGBW filters and microlenses.

On the top-left corner there are some experimental silicon photomultipliers and SPAD diodes. These I plan to measure for fun and I promise to post the results in any of the two blogs.

Unfortunately, this chip wouldn't yield tons of publicaiton work, apart from the core ADC architecture and comparator. To test the ADC one needs a whole bunch of other fast readout blocks, which in the end are not something novel, but yet, one needs them and designing these take time. Finishing up this test system was a lot of work and I realize that it might be a bit risky and ambitious to be doing this as part of a doctorate. What if it fails to work because a state machine had an inverted signal somewhere? Or the home-made ESD and pads suffer from latch-up? Or the LVDS driver CMFB is unstable and I cannot readout data out? Or there is a current spike erasing the content of the SRAM? Or, or, or ?

We university people don't have the corporate power to tapeout metal fixes twice a month until we're there. I probably have another two or three chip runs for my whole doctorate. It may therefore be better (and more fun) to stick with small but esoteric modules, which one can verify separately and have time to analyze in detail. But hey, I'll quote a colleague here: "It is what it is, let's think how we can improve things."

Let's wish good luck with the production and see what we end up with.

Date:Sat Apr 16 13:29:13 CET 2016