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I thought that it might be a good idea to share the visuals from ISSCC with you and give short comments on some of the works I found intriguing from the CIS section. Please disregard my punctuation and language, this initially used to be a brief e-mail to my coworkers, however, I thought, "Why not get a free post out of it?" :) Unfortunately I am not allowed to upload any of the materials I sent them, thus you will have to refer to the original papers at IEEE XPlore.
Some new imaging materials made it to the CIS section this year, in particular there were two intriguing papers from Panasonic presenting an organic photoconductive global shutter imager with 120dB DR and speed of 60fps at almost 1MP with quite low read noise too!!! Also, note - they report a 600ke- FW capacity for a 6x6um pixel - impressive! There was a live demonstration of the imager, which looked rather sneaky as they used a very bright light (car headlamp) for illumination, which suggests low quantum efficiency of the sensor. Unfortunately, Panasonic did not provide any further comments on their work, apart from what is there in the slides. Some people asked direct questions on QE and process - answers were simply "I don't know".
The original paper is entitled as: An Over 120dB Simultaneous-Capture Wide-Dynamic-Range 1.6e- Ultra-Low-Reset-Noise Organic-Photoconductive-Film CMOS Image Sensor
Jan Bogaerts from CMOSIS presented an almost 400MP imager for airborne mapping, working at 1fps in 14-bit mode. Really impressive work from an engineering point of view. I managed to get hold of the sensor which has the size of a large smartphone, and one can clearly see the 6x3 pixel die blocks stitched together. The imager has no color filters, however the whole system uses 6 additional CCD sensors for color information extraction and a quite sophisticated optical stabilization system.
For more details refer to: 105x65mm2 391Mpixel CMOS Image Sensor with >78dB Dynamic Range for Airborne Mapping Applications
David Stoppa presented two works on SPAD imagers, one of which you can find in the visuals. The other presentation was given at a forum and have no electronic slides to show. The impressive point within these SPAD projects is that they report a read noise as low as 0.22 e-. This in terms allows them to measure photon shot noise and observe its poisson distribution! Theoretical physics works!
Paper title: A 64x64-Pixel Digital Silicon Photomultiplier Direct ToF Sensor with 100MPhotons/s/pixel Background Rejection and Imaging/Altimeter Mode with 0.14% Precision up to 6km for Spacecraft Navigation and Landing
TSMC, Toshiba and NHK presented works focusing on the ADC and analog signal processing in 3D stacked chips. Although, NHK and Toshiba present a refined version of their old cyclic ADC architecture, it is still worth noting that they report pure conversion time speeds of less than 0.9us, with relatively low energy per conversion. TSMC show detailed schematics of their Gray-coded ramp ADC, worth having a deeper investigation.
Paper titles accordingly: A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA; A 1.1um 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters
In addition TSMC's work features an interesting readout technique named "Negative Substrate Bias Readout" - In simple words: by biasing the substrate negatively they can use 1.5V supply for the readout and still get 3.3 volts for the pixel diode - thus saving power and not compromising SNR. This technique is enabled by the 3D stacking as the pixel array is a separate die, which can have a separate substrate bias.
Ref: A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias
For more information and details around the presented works, I suggest having a further look at the digest materials here.
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