^{-}▲ about & FAQ

**TDI CCD and TDI CMOS Signal-to-Noise Ratio and Dynamic Range**

I was skimming through this paper from IEEE Transactions on VLSI Systems. In Section II A, the authors give a brief introduction on TDI CMOS image sensors and the basic SNR and DR dependence on the number of TDI stages $N$. What stoke me was their claim that the dynamic range of a CMOS TDI sensor decreases with the number of stages. While this holds for a CCD TDI image sensor, things stand completely different for a CMOS imager. This wrong statement is also my main motivation for this post.

**1. SNR and Dynamic Range (DR) for a TDI CCD Image Sensor**

In a CCD TDI imager, the pixel has to have a large full well capacitance in order to be able to hold the final accumulated output signal. Therefore, the CCD's full well has to be maximized in as to increase the dynamic range and avoid saturation/blooming problems.

Intuitively the signal-to-noise ratio would be equivalent to: $$SNR = 20log\Bigg(\frac{\sqrt{N}(i_{ph}t_{s})}{\sigma_{total}}\Bigg)$$ and the dynamic range of a CCD TDI sensor would be: $$ DR = 20log\Bigg(\frac{q_{fwmax}-(N i_{dc}t_{s})}{\sqrt{N}\sigma_{total}}\Bigg) $$ Therefore the DR would be limited by the charge handling capacity of the output CCD channel, which means that with a CCD we would like to have as large full well as possivle. One might observe that in the case of CCDs, the dynamic range would indeed be reduced with the increase of the number of stages due to the total noise addition at each stage. This however is not the case with a CMOS image sensor as we shall see soon.

**2. SNR and Dynamic Range (DR) for a TDI CMOS Image Sensor**

In a TDI CMOS sensor unlike CCDs, the pixel has to be designed only to handle the maximum full well capacity needed for the expected operating integration time per line.

As the integration time is low, the FW capacity can be low and the pixel constructed with high conversion gain. This also reduces noise (maximizes signal swing) and in some sense is relaxing the readout noise requirement, bar the fact that TDI in CMOS imposes tough (very low) noise requirements on the readout as the readout noise adds with the square root of the number time delay integration stages.

The signal to noise ratio as well as the dynamic range for a CMOS TDI sensor would therefore be: $$ SNR = 20log\Bigg(\frac{\sqrt{N}(i_{ph}t_{s})}{\sigma_{total}}\Bigg) $$ $$ DR = 20log\Bigg(\frac{N q_{fwmax}-(N i_{dc}t_{s})}{\sqrt{N}\sigma_{total}}\Bigg) $$ The total full well capacity equals to the sum of the separate pixel full wells $FW_{tot} = \sum\limits_{i=1}^n FW_{pix_n}$, so the total full well is practically only limited by the accummulators, which can be either implemented in the analog or digital domain. With digital accummulators the total FW can in general have no limits.