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A precision DIY Scanning Tunneling Microscope

Last weekend I paid a visit to Kris at the University of Bath. She is currently finishing-up with her doctoral studies and invited me to pay a visit to her lab and the materials group's DIY scanning tunneling microscope. During that weekend we scanned a few Silicon 111 wafer samples and injected Toulene molecules on the wafer.

I was quite impressed that the tunneling current noise floor of their microscope was in the order of a couple of hundred femto amperes, which is quite impressive for a measurement system operating at room temperature. It seems like they were using a commercial low-noise programmable gain amplifier produced by the German company Femto. It was quite tempting to open the amplifier box and see what's inside. I doubt that there is a custom OPA in it, but I really wonder which commercial chips did they use and what was this low-noise PGA feedback configuration used. Anyway, here are some fancy pictures of my visit and this has now inspired me to run an investigation on the OP and low-noise needle amplifiers used.

Outer look of the STM, the long pipes are manipulating shafts used inside the chamber; the turbopump as well as the piston pumps can be seen on the left side of the machine
Different angle, the turbopump as well as the head chamber are seen in the centre of the image
Here is the scanning head, together with a sample attached. The head is using piezo elements for micropositioning and scanning in both ways
The low-noise programmable gain amplifier manufactured by Femto Gmbh, note that the gain is changed by turning the rotary switch and not electronically
An STM image of the Si 111 sample, we can see the individual atoms as well as some impurities. Seems like the Czochralski method is indeed a brilliant casting technique

Besides the immense pressure/vaccuum required for this machine to work, the electronics behind it is fascinating. A PLL and all other sorts of regulating loops to precisely control the needle. The piezo elements have a natural vibrating frquency for which it should be corrected. A needle with passing fA currents though the sample, very low-noise programmable gain amplifier with filters and a 16-bit analog to digital converter. Moreover some digital image acquisition and needle vibration correction algorithms are used to reconstruct the images. Simply a symphony of virtuoso circuits!

MORE IMAGES IN THE GALLERY HERE

Date:Tue May 09 15:00:23 CET 2015

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A few useful functions for Virtuoso layout

I am waiting for a simulation to finish and am a bit bored having done layout whole day. Let me post some very simple but useful SKILL finctions for the layout editor of Cadence's tools.

The first one I use regularly adds a specific layout instance when invoked. I have binded it to various keys and thus can add cells from my own common library, e.g. VIA_M1_M2_min, VIA_M2_M3_min, M1_PO_min, M1_PO_minx2, M1_AA_min etc...

Now you might argue that there are normally provided p-cells for thus purpose, which is true. However, for the image sensor processes I use, this "feature" normally is not provided by the foundries. Or at least, the ones I've used so far haven't got any p-cells. A quick solution is thus having own cell library and adding layout views from it.

I also kind of like that freestyle layout drawing as it gives you the freedom to do "virtuoso stuff", which you normally can't do with p-cells, or it is tedious to set. Besides, p-cells rely on SKILL and Virtuoso's ROD engine, if that setup somehow fails, then the whole design can not be "compiled" / "viewed". Anyway, here is how I instantiate my cells:

;A function to add specified layout instances

procedure(placeInstance(lib cell view "t")
 leSetEnv("instLibName" lib)
 leSetEnv("instCellName" cell)
 leSetEnv("instViewName" view)
 hiRegTimer("hiToggleEnterForm()" 1)
 leHiCreateInst()
)

;Binding it to a key:
hiSetBindKey("Layout" "Ctrl Alt1" "placeInstance(\"commonLib\" \"M1_M2_min\" \"layout\")")

You can set hiRegTimer("hiToggleEnterForm()" 1) to 0 if you want the enter form to appear and not be auto-minimized, or on the other way around '1' would auto-minimize the window and you are good to go.

Another quick and handy layout bindkey function is the toggle layout: Here is how we can toggle layer visibility, I know there's tons of resources on that, but still may be useful to have a yet another source.

;Toggle layer selectability procedure for metal layers

procedure( toggleMetal(num "x")
  let(((metlay list(sprintf(nil "M%d" num) "drawing")) )
    if(leIsLayerSelectable(metlay) then
      leSetLayerSelectable(metlay nil)
    else
      leSetLayerSelectable(metlay t)
    )
    hiRedraw()
  )
)

We can set it to an arbitraty layer defined in our techlib by minor corrections. We can even choose to toggle schematic editor layers.

Alternatively, we can also toggle visibility which is one of my favorite functions:

;Toggle layer visibility procedure

procedure( CCStoggleNW(num "x")
  let(((metlay list(sprintf(nil "NW" num) "drawing")) )
    if(leIsLayerVisible(metlay) then
      leSetLayerVisible(metlay nil)
    else
      leSetLayerVisible(metlay t)
    )
    hiRedraw()
  )
)

I guess the most important stress in this post, and in doing fast and efficient layout (bar good floorplanning and thinking in advance), is the good set of bindkey functions. Try to use the mouse as less frequent as possible, i.e. only for drawing or zooming-in-out.

Date:Tue Apr 28 17:45:49 CET 2015

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"Alchymia" in circuit design

I stumbled upon an interesting book - The Collected Papers of Lewis Fry Richardson. Richardson was an English scientist of "everything" - maths, physics, psychology, meteorology... actually a pioneer of modern day mathematical techniques of weather forecasting.

Now all that is great, but what got my attention is the following figure: (I hope reprinting figures from Richardson's papers from 1930s is not a severe copyright violation)

This all looks to me like some crazy alchemistry in circuit design. No matter how many times I tried to read this paragraph it all simply does not make any sense at all. It really is fascinating how great scientists in the past tried all sorts of crazy ideas (including the addition of an electric eel to an RLC circuit) to see "if something great would happen".

But wait, there is even more:

It all smells some deep alchemistry happenning around. But hey, if I can, why not?

Date:Tue Apr 19 14:07:40 CET 2015

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Fun with the parallel (LPT) port

Recently I participated in an applied electronics seminar at the University of Ruse, which aimed at promoting the electronics "sub-subject" to high school and first-year students. I decided to talk a bit about CMOS integrated circuits and let the students play with the parallel port of a PC and make them play some music over the LPT port through an R2R DAC. It ended-up being quite fun, let me briefly show you what I used and how easy it was :) Below you can watch a video with the very first enlivening of the "player".

I used randomly picked (not even exactly R and 2R) resistors to form an R2R ladder which I then connected to the parallel port's 8-bit data bus. For the rest (LPT control) I used octave and the instrument-control package provided to directly access the LPT port and dump vector streams to it. Unfortunately "instrument-control" does not provide us with sampling rate functions as this is purely OS/octave handling dependent. Nevertheless we can measure it and provide interpolated samples to the DAC to suit our needs, or to keep a somewhat reasonable sample-time base close to the real one in the files which we are playing. Here is a minimalistic code to make things work.

%clc;
%clear all;

pkg load instrument-control

[y0 rate bits] = wavread("/usr/share/skype/sounds/CallRingingIn.wav");

N = 8;

y=round(y0*(2^N/2)+(2^N/2)); % scale to 8 bits 0-255 and round to nearest integer

nSmpl = length(y);

pp = parallel("/dev/parport0", 0);

for k = 1:nSmpl
pp_data(pp,y(k));
%pp_data(pp,255);  % flash port to measure LPT port sampling rate
%pp_data(pp,0);
end

pp_close(pp);

Also, here are some pictures from the seminar we organized.

ROUTE TO THE PICTURE GALLERY

Date:Tue Apr 16 10:02:34 CET 2015

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Ideal ramp generator

Why not go back to basics and show how an ideal ramp voltage generator can be implemented in Virtuoso by using simple ideal components from the analogLib library.

We can use a voltage controlled current source (vccs) driving current into a capacitor and forming a negative feedback and employing a second voltage source which sets the maximum ramp voltage level. An ideal switch is ised for capacitor discharge (reset), and as long as we have the switch turned off our generator starts ramping.

The slew rate can be controlled by changing the maximum deliverable current by our vccs. Some cell parametrization seems useful in our case. You can get this component here.

Date:Tue Feb 06 11:53:21 CET 2015

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